FS20

1

a)

Just basic mistakes, I could have done better.
Remember to use $X+XY=X$

b)

Not simplified enough. $\bar{B}+BC=\bar{B}+C$ using expansion with $\bar{B}+\bar{B}C+BC=\bar{B}+C(\bar{B}+B)=\bar{B}+C$.

2

b)

Here create an always block that updates the value of curVal with the posedge clk.

d)

Assign in Always

A wire cannot be assigned inside an always block → must be driven by continuous assignment.

wire a;
always @ (*) a = b; // this is a compile error

3

3.2

This is an edge-detector!

6

a)

There is only EX/MEM → EX forwarding here!

In cycle 6-7 it looks like instruction 3 is waiting for MEM/WB forwarding from #1 to #3 for register R1. But it’s actually waiting for instruction 2!
The forwarding there is not forwarding, it’s just register forwarding (writing in first half/ reading in second).

Note Data forwarding includes flag forwarding (condition registers).
So also EX/MEM → EX zero flag forwarding.

b)

Fill the table with the NOP stages (it goes through all of them normally).

7

a)

read carefully
→ distinguish between “if pipelined, then this, if not then that”

10

a)

Each causes 4 stall cycles, so at the end of stage 5 the branch is evaluated!
Not 4 stall cycles ⇒ end of stage 4.

b)

I completely miscounted.
Each conditional branch is executed 6 times per loop (5 times taken, then once at the end).
Thus total of $1+(5\ast 3+1)\ast 5+1+1=98$ instructions in total.

c)

Here, the conditional branch instructions are $(5+1)\ast 5+1=36$.

11 VLIW

a)

VLIW wants →

• reduce overall hardware complexity
• simplify hardware inter-instruction dependence checking
  • yes, since the compiler takes care of that

b)

Stupid mistake scheduling.