FS25

2

2.1)

Blocking vs. Nonblocking

• blocking is in series
• non-blocking completes in parallel

2.2

It’s 75/180 Hz, not the other way around.

3

3.1

Forgot a self loop.

Note that in cases like this you can just spam together many input combinations into one arrow.

5

a)

Branch Prediction Stalls:
It says “branch prediction → predicts all branches as taken, address of the PC becomes available after the decode stage”

• since it’s always taken → PC+4 is not the next address
• we actually need to wait for the bne or beqz to resolve.
• Therefore, one stall, until it’s in ID stage.

Always Taken prediction

Always taken → requires waiting for ID until the new PC is available!

ID Stage
Then in the official solution, 2 instructions are in ID in the same cycle → meaning we have some kind of “waiting” in the latches between stages

• beqz can enter ID while andi is still stalling before EX
  → If we do make this assumption, note it

c)

Write optimised Assembly from C code.

This was pretty easy, I just didn’t get it. Just use mult and reorder the lw to not stall → this gets us stall free code.

7 Memory Potpourri

6T SRAM cell, four T for access, two for storage

• FALSE, it’s 4T for storage (2 couples NOTS = 2 * 2 T)
• And the other 2 for access

Flash Memory has higher cost per MB than hard disk
→ TRUE, Hard disk is probably cheapest after tape

8 VM

The multiple choice → single choice!

a)

1. Primary advantage of VM → allows a programs logical address space to be much larger than available physical memory
2. Page Fault
   1. Page in physical memory but no mapping yet → also a page fault
   2. occurs with shared libraries (already loaded, but not by this program yet)

b)

Just draw some random comparators and hook them up.
Don’t forget to also choose between old and new depending on virtual address.

9

c)

We fetch $A,A+1,A+2,A+3,A+4$ with $N=2$.
Thus coverage is 5/3, not 4/3 (forgot to include $A$ itself originally)

10. VLIW

b)

Divide only by the number of VLIW operations, not by the total number of possible ops!!!!

It’s 7/5 not 7/30!!!

d)

The energy usage is more complicated than what I did. We first get the avg. power per VLIW.

Then $5\ast N\cdot \frac{1}{10^{9}s}$ as it’s 1 GHz.

11. Caches

Here, the compiler apparently does not use registers, all accesses, even the stores are cache relevant.

a)

Since A, B → set 0 and C → set 64 (only 128 * 4B / 32B blocks = 16 sets), thus no overlap between {A, B} and {C}.

Therefore we have 3 misses per 8, thus 3/40 (as 5 cache reqs per iteration)

b)

Now C is also mapped down to set 0 (since E = 1110 and thus 13 bits of 0)
Now hit rate is only A (and C store), so $2\ast 7+1$ hits from A. C hits once per iter
Thus hit rate $40-(2\ast 7+1+8)=40-(15+8)=17/40$.