2. Combinational Logic

Now that we understand basic logic gate structure, we can combine them to build more complex structures.

To do so, we will build a framework for specifying our circuit.

We will first approach combination logic, which is memoryless, i.e. the ouputs are strictly dependent on the combination of input values being applied right now.

2.1 Boolean Algebra - Foundation of Logic Design

2.2.1 Basic Operations

There are three fundamental operations in boolean algebra.

Operations Boolean Algebra

1. Not / Complement $\bar{A}$
2. AND $A\cdot B$
3. OR $A+B$

Boolean algebra is:

• closed with regards to those operations.
• commutative
• each have an identity (0 for OR and 1 for AND)
• distributive law holds
• Complement
  • OR on the complement $A+\bar{A}=1$ gives AND neutral
  • AND on the complement $A\cdot \bar{A}=0$ gives OR neutral

2.1.2 Duality

By swapping AND with OR, 0s with 1s but not any literals or anything else, we still get a valid boolean equation.

Example:

• $\overline{(A\cdot B)}=\bar{A}+\bar{B}$ is equivalent to $\overline{A+B}=\bar{A}\cdot \bar{B}$ which is the dual of De Morgan’s law.

2.1.3 Useful Laws

Boolean Algebra, Useful Laws

1. Operations with $0$ and $1$:
2. $X+0=X$ $X+1=1$
3. $X\cdot 1=X$ $X\cdot 0=0$ (dual of the previous)
4. Idempotent Law
5. $X+X=X\cdot X=X$
6. Involution Law
7. $\overline{(\bar{X})}=X$
8. Law of Complementarity
9. $X+\bar{X}=1$ and $X\cdot \bar{X}=0$
10. Commutativity
11. Associativity
12. Distributivity

Simplification Theorems

Useful to remember!

1. $X\cdot Y+X\cdot \bar{Y}=X$ and it’s dual $(X+Y)\cdot (X+\bar{Y})=X$
2. $X+X\cdot Y=X$ and $X\cdot (X+Y)=X$
3. $(X+\bar{Y})\cdot Y=X\cdot Y$ and $(X\cdot \bar{Y})+Y=X+Y$

2.1.4 Standardised Function Representations

Using canonical representations (SOP and POS, equivalent to DNF and CNF), we can communicate a components operation exactly, which allows computer aided design or automation.
One function can have many hardware representations, but we standardise it’s form using SOP or POS.

The standard forms:

• Sum of Products (DNF)
• Product of Sums (CNF)

Some vocabulary:

• Implicant: product term that implies the function (i.e. if the product term is $1$, the function is $1$). Can be single literal or combination ANDed together.
• Minterm: product term (AND term) that includes all input variables (either in true or complement form). A Minterm is $1$ for exactly $1$ row of the truth table.
• Maxterm: sum term (OR term) that includes all input variables. (Is $0$ for exactly one row).

The SOP form of some function given as a set of minterms.

2.1.5 Sigma Notation (Standard)

The boolean table is a unique signature of our function, but it is expensive. We can give the SOP or POS form as a standardised way to communicate the function table more efficiently.

We can then use logic minimisation techniques to automate it’s actual implementation in hardware.

We can then give the function in either SOP form

$$\sum m(3,4,5,6,7)$$

or POS form

$$\prod M(0,1,2)$$

which are “complementing” each other as is clear. There are some useful rewriting rules.

1. Minterm to Maxterm / Maxterm to Minterm
   1. Rewrite the shorthand to use Maxterm and replace indices by those not already used (see above)
2. Expansion of $F$ to expansion of $\bar{F}$
   1. $F(A,B,C)=\sum m(3,4,5,6,7)$ gives us $\bar{F}(A,B,C)=\sum m(0,1,2)$
   2. $F(A,B,C)=\prod M(0,1,2)$ gives us $\bar{F}(A,B,C)=\prod M(3,4,5,6,7)$
   3. “invert” the indices
3. Minterm of $F$ to Maxterm of $\bar{F}$*
   1. $F(A,B,C)=\sum m(3,4,5,6,7)$ gives us $\bar{F}(A,B,C)=\prod M(3,4,5,6,7)$
   2. $F(A,B,C)=\prod M(0,1,2)$ gives us $\bar{F}(A,B,C)=\sum m(0,1,2)$
   3. Use same indices but go from max- to minterm

2.2 Basic Combinational Blocks

There are foundational building blocks of logic which enables reuse in order to facilitate building more complex systems: Decoder, Multiplexer, Full Adder, PLA, etc…

2.2.1 Decoder

Inputs n Outputs $2^n$
The decoder is basically a “pattern detector”.

Such a decoder is useful in memory address finding or decoding the instruction in the ALU.

2.2.2 Multiplexer

Input n Output ${\log }_{2}n$
Selects one of the $n$ inputs to connect to the output, based on the select signal.

We can use multiplexers as “lookup” tables to perform logic functions for example. The following is an example of a 3 LUT.

LUT

$3$-LUT can implement any $3$-bit input function.

Note, we could use a decoder in the same way, by ORing between the outputs for which we want it to evaluate to $1$ (see slide 103 in the second lecture).

2.2.3 Full Adder

The full adder carries out binary addition with a carry bit.
Example: $a=1,b=1,c=1$ so adding $1+1$ with the carry bit set gives us $1$ and $1$ is carried, $11=3$ in binary so this indeed works out.

We can chain the adders in order to add multiple bits, by daisy-chaining the carry bits. This is called a ripple carry adder.

This does have the problem of latency, which is why we would use more optimised circuitry for longer additions.
We can instead use specialised logic for fast carry calculation and perform addition in parallel.

2.2.4 Programmable Logic Array (PLA)

By using a PLA, we can simply the design/implementation of a function in hardware.
We use a column of ANDs (negating as needed) and connect them to ORs as output. This is exactly SOP form implemented.

We can implement a full adder as a PLA, as seen here:

We wire up the implicants to the OR gates and get the outputs.

2.2.5 Comparator

Checks if two $N$-input values are exactly the same by wiring each pair of inputs into an XNOR gate and summing up with an AND.

2.2.6 Arithmetic Logic Unit (ALU)

The ALU takes a “word” as an input which decides which operation to perform on inputs (as defined in the instruction set).

2.2.7 Tri-State Buffer

Enable gating of different signals onto a wire.
While the E is low, the output stays the same as before, once we set E high, it is updated from the input.

For example, when we have a gate between CPU and memory, we want to only allow one device to write to it at the same time.

We can also build a multiplexer in this way, by configuring the enable in such a way that it enable the correct input for each combination:

2.3 Logical (Functional Completeness)

We can implement any logic function we wish with a PLA, which consists only of AND, OR and inverters. This is because the set of gates {AND, OR, NOT} is logically complete.

Any function can be rewritten in SOP or POS form.

NAND is also logically complete, as we can easily show by expressing {AND, OR, NOT} in terms of only NAND gates.

2.4 Simplifying

Even though we can use SOP to implement any logic function in a PLA, this is often inefficient. We can use way less gates.

2.4.1 Uniting Theorem

If two product terms differ only in one variable (variable and it’s complement), the variable can be eliminated:

$$A\cdot B+A\cdot \overline{B}=A$$

We identify pairs of min-terms from which we can eliminate variables.

2.4.2 Don’t Cares

By implementing “don’t cares” as $X$ in the truth table, we can reduce complexity by a lot. We go from a giant truth table to a 4 row one.

This is essentially the uniting theorem in “graphical version”. We group a number of min-terms together while building the function table, essentially eliminating variables.